Three-Dimensional (3D) stacking of semiconductor substrates is a promising technology for manufacturing devices with improved performance and power consumption while maintaining a low form factor. Over the past few years, numerous technological advances in the field of 3D technology have been reported. However, reliability and the high cost of manufacturing remain the main issues that prevent 3D technology to be adopted in volume production. These issues are mainly associated with the bonding of semiconductor substrates and more specifically with the material selection and bonding methods used therein.
One of the most attractive volume production methods for bonding semiconductor substrates is the Copper to Copper bonding, hereinafter referred to as Cu—Cu bonding. Copper is favored by the semiconductor industry over other metals, e.g., Al, Au, because of its superior electrical conductivity characteristic and low cost, when used in large volume manufacturing. On the other hand, Cu has a tendency to develop oxides and other contaminants during manufacturing. Therefore, in order to achieve a successful bond between the semiconductor substrates, the oxides and contaminants formed on the Cu surface need to be removed. In principle, Cu—Cu bonding is achieved through thermo-compression, hereinafter referred to as TC-bonding, whereby the Cu surfaces of the semiconductor substrates are brought into contact applying force (pressure) and heat simultaneously. In order to break through the oxides and contaminants formed on the Cu surfaces, TC-bonding typically requires a temperature of around 300 to 450° C. coupled with a pressure exceeding 300 MPa for duration of around 20 to 60 min. As a result of the high temperature and high pressure applied during TC-bonding, stress related failures might occur in the bonded semiconductor substrates, thereby compromising reliability and hence yield of the 3D device manufactured. Moreover, the conditions for performing TC-bonding, limit the applications that could benefit from Cu—Cu bonding. As an example, a memory chip containing DRAM or SRAM cells will not be able to withstand the temperature and forces applied during thermo-compression bonding.
In the context of TC-bonding, U.S. Pat. No. 7,973,407 describes a number of 3D stacked substrate arrangements and methods for minimizing or preventing Cu oxidization, thereby enabling low temperature and low pressure TC-bonding. More specifically, the process flows described therein minimize or prevent Cu oxidization by quickly bonding the semiconductor substrates after a chemical cleaning step has been performed, thereby reducing the time that the Cu surface is exposed to the atmosphere and thereby minimizing Cu oxidization. The proposed process flows are carried out in a controlled process environment and requires complex processing steps, for example the chemical cleaning step, that are incompatible with current high volume semiconductor manufacturing processes. As a result, overall cost of manufacturing is increased while throughput is reduced.